Xilinx SDK is not updated by μblaze parameters

I have modified the "system.mhs" file as follows :begin microblaze // some lines of code PARAMETER C_PVR = 2 PARAMETER C_PVR_USER1 = 0x02 PARAMETER C_PVR_USER2 = 0x0bb35//some lines of codeEndwhen i build the hardware in Xps and export to xilinx SDK i do not see these parameters updated in xparameters.h. any hints ?...Read more

Creating a custom pcore for Xilinx ISE 14.7?

A bit of a general question, but what is the most popular/common/easiest way of creating a custom pcore?I have seen some examples and they were mostly done on Matlab and since I do not have Matlab anywhere, I am a bit lost here. There has got to be a proper way of doing without it!Thank you in advance!!!...Read more

xilinx - Maximum path delay in a simple combinational circuit

I want to calculate the maximum path delay for a combinational circuit in Xilinx ISE. I'm familiar with the sequential circuits and I know how to work with timing constraints and the timing reports generated after P&R. But with no clock in the design, I do not know what should I do? Is it necessary to add clock in every combinational design so that it can be figured that how much the maximum path delay is?For example, for the following VHDL code of a full adder, how can I measure the maximum path delay?library IEEE;use IEEE.STD_LOGIC_1164.A...Read more

vivado - Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?

Consider an AXI4 Interconnect on the PL (FPGA) side. When I double click to see the available options, there is a tab in Slave interfaces. Containing the following options. What is the purpose of enabling register slice? Does outer refer to the L2 cache? And what does Auto mean? What is the purpose of enabling the Data FIFO? For burst transactions? Doesn't the DMA controller have it's own FIFO?...Read more

xilinx - Memory regions not displayed in 'lspci -vv' while using 'AXI bridge for PCI express Gen3.0 subsystem'

We are developing a system with a custom processor, Microblaze and some peripherals in VC709 FPGA using Xilinx Vivado. We are using two 'PCIe : BARs' in 'AXI Bridge for PCI express'.Initially the command 'lspci -vv' used to show memory regions in the Ubuntu teminal.$ lspci -vv 0a:00.0 Memory controller: Xilinx Corporation Device 7038 | 0a:00.0 Memory controller: Xilinx Corporation Device 7018 Subsystem: Xilinx Corporation Device 0007 | Subsystem: Xilinx Corporation Device 0008 ...Read more

libpcap - pcap.h file in Xilinx Vivado HLS

I have used the pcap.h header file to parse a pcap file in Linux. The program compiles and parses the packets correctly. However, I want to put the same logic on a FPGA, for which I am using the Xilinx Vivado HLS tool. I am facing issues with the linking of pcap.h file in Xilinx Vivado. So, now I have two options:1. How to link an external library in Xilinx Vivado HLS ?2. If 1. is not possible, I would want to know if it is possible to parse a pcap packet without using the pcap.h header file?...Read more

xilinx - Yocto: cannot build meta-mono

I'm trying to build an embedded system with yocto poky. My layers are: BBLAYERS ?= " \ /home/dev/microzed/meta \ /home/dev/microzed/meta-yocto \ /home/dev/microzed/meta-yocto-bsp \ /home/dev/microzed/meta-xilinx \ /home/dev/microzed/meta-mono \ "with git clones: git clone -b master git://git.yoctoproject.org/poky.git ~/microzedgit clone -b master git://git.yoctoproject.org/meta-xilinx ~/microzed/meta-xilinxgit clone -b master git://git.yoctoproject.org/meta-mono ~/microzed/meta-monowith bitbake core-image-minimal it all compiles and runs ...Read more

xilinx - mtd-utils error during yocto build

I'm trying to build Petalinux with meta-swupdate from https://github.com/Xilinx/yocto-manifests and https://github.com/sbabic/meta-swupdate. I followed the directions for Peatlinux manifest. The command to build it wasTEMPLATECONF=/home/someuser/projects/petalinux-build-system/sources/meta-petalinux/conf sources/core/oe-init-env-build petalinux-build-envbitbake petalinux-image-fullEverything worked. Then I added a meta-swupdate layer to the bblayers.conf and rebuilt (bitbake petalinux-image-full). This is where the I'm having issues. During the...Read more

xilinx - DISTRO 'poky' not found. Please set a valid DISTRO in your local.conf

New to Yocto. Trying to build an image for Xilinx Zynq. Followed instructions on https://github.com/Xilinx/meta-petalinux. Don't need everything there, so removed some of the layers. When I execute bitbake zynq-generic I get the following error: $ bitbake petalinux-imageERROR: OE-core's config sanity checker detected a potential misconfiguration. Either fix the cause of this error or at your own risk disable the checker (see sanity.conf). Following is the list of potential problems / advisories: DISTRO 'poky' not found. Please set a v...Read more

xilinx - Yocto u-boot Custom Commands

What is the correct way of adding custom commands to u-boot in a Yocto setup (currently using Petalinux 2016.4 by Xilinx)?Should I add the relevant source files to the u-boot source through a recipe/patch, to be included in the compilation of u-boot?Is there a better way to do this during development to get a faster turn around.In what folder should the code be placed - under u-boot/board or added to u-boot/commands?Thanks...Read more

xilinx - Using ROOTFS_POSTPROCESS_COMMAND to add function that copies files

What I used to do this was use ROOTFS_POSTPROCESS_COMMAND variable to add my own shell script functions.I needed to append the petalinux-user-image in meta-plnx-generated so in my meta-user layer, I created the following file: petalinux-user-image.bbappend:inherit core-imageROOTFS_POSTPROCESS_COMMAND += "my_install_function; "my_install_function(){ echo "hello" > ${IMAGE_ROOTFS}/hello.txt}What I am trouble with is how do I add files to the ${IMAGE_ROOTFS}. I can remove/move files/create files, but can't seem to copy files from my meta-use...Read more