electronics - Starting FPGA Programming

I want to start FPGA programming. I don't have any knowledge at all about how FPGAs work and such. I would like to get a development board, not too expensive, but it should have at least 40 I/O pins. Anything up to $300 is OK.I decided that I want to program in Verilog. I am not sure about the following:How will my compiled 'program' be stored on the chip? I would guess the chip has some kind of EEPROM to save my program, but from what I have read, it is apparently stored in RAM. I want my program to remain on the chip (or to be loaded somehow)...Read more

fpga - During implementing FIFO buffer code for serial communication taking too much time

I am a new bee in VHDL coding. I am currently working on starter kit spartan 3e. I have written a code for transmitting 5 bytes to PC and receiving 4 bytes. Now I have to add fifo buffer before transmitting and after receiving bytes.I have written code( taken from Pong P Chu) also but not working. Its taking too much time for synthesis. Please tell me where I am going wrong.Thanks in advance. entity fifo is generic ( B : natural :=32; --------------------------------------------------- number of bits W : natural := 16 ------...Read more

fpga - Whether combinational circuit will have less frequency of operation than sequential circuit?

I have designed an algorithm-SHA3 algorithm in 2 ways - combinationaland sequential.The sequential design that is with clock when synthesized giving design summary as Minimum clock period 1.275 ns and Maximum frequency 784.129 MHz.While the combinational one which is designed without clock and has been put between input and output registers is giving synthesis report as Minimum clock period 1701.691 ns and Maximum frequency 0.588 MHz.so i want to ask is it correct that combinational will have lesser frequency than sequential?As far as theory i...Read more

xilinx - reading FPGA's block RAM from pc

I am using Xilinx ISE 14.7 synthesizer. I am able to initialize my BRAM with a .coe file and access it. Also I can update it with new .mem file using data2mem tool and update my bit file. Here I have configured it as ROM.My problem is, I don't know how to store the BRAM contents to a file. I am using Single port block memory from the core generator. I am configuring it as RAM. I want to write data to it and access it later. I didn't find any relevant post stating this. May be its only me who didnt find a way to save the contents to a file. For ...Read more

fpga - Xilinx Virtex6 block ram width

I'm confused about Virtex-6 BlockRAM.I want to implement a BRAM with 15 bit address (32,768 words) and 12 bit write and read data per word. When I explore the implemented design, I founded that 12 BlockRAM are used for this. Does this mean each BRAM in a Virtex-6 has 1 bit data?!What is the data width and capacity of each BlockRAM in a Virtex-6?...Read more

fpga - How do I read the status register of a Virtex 5 in a JTAG chain?

I'm working on an XUPV5-LX110T and I'm trying to read the status register over JTAG. I'm getting incorrect data, but I can't see why. I seem to be getting all zeros. I suspect it has to do with the order of the JTAG chain, but I'm not sure how I should adjust the order of the commands I send. I know the TMS pits will change the state of all the devices on the chain, but how do you shift in data to the FPGA when it's the last device on the chain?...Read more

fpga - ChipScope Error - Did not find trigger mark in buffer

Has anybody mentioned data errors, trigger error or upload errors in ChipScope?I'm using ChipScope (from ISE 14.7) with the IP core flow. So I created 15 different ICON IP cores as ngc files and wrapped them all in a VHDL module. This module chooses by generic with ngc file should be instantiated. So I can easily choose the number of active VIO/ILA cores.Currently my project has 2 VIO cores and 5 ILA cores, utilizing circa 190 BlockRAMs on a Kintex-7 325T (>400 BlockRAMs in total). When a trigger event occurs, I get sometimes the warning Did no...Read more

Look-Up Table division synthesizable in an ASIC/FPGA design? Makes any sense?

I was studying the ways to make an efficient FPGA project (toward to become an ASIC design) which include division operations of simple 32 bits binary numbers.I have found that the most expedite way to do it, is using LUT (Look-up table), than generating a complex division logic. That's fine, however, when I think about ASIC I imagine a physical microchip, with digital logic inside, I can't imagine to put a whole table inside to produce the division. I can understand it makes sense in an FPGA because it has a lot of resources including on-chip ...Read more

fpga - How to use Quartus to optimize combinational logic?

I am using Quartus to synthesize a combinational circuit to FPGA. Right now I want to get the best possible maximum frequency without considering the resource consumption. The current critical path is composed by a sequence of multiplications like this:res = a * b * c *dI am wondering whether it is possible for Quartus to automatically generate an equivalent combinational logic that has shorter critical path like this:ab = a * bcd = c * dres = ab * cdWhich have only two multipliers on the critical path. I found an online document from Quartus...Read more

fpga - Any example useage of a BSCANE2 primitive in Xilinx 7 series? (using the JTAG port to configure user design)

I've looked over the info on BSCANE2 in http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf (pg 169 7 Series FPGA Configuration Guide) and I can't quite figure out how to use it based on that descriptions.I want to be able to use the JTAG port on the KC705 board to shift in some configuration data for our design. I think (based on the description there in the user guide linked above) that the BSCANE2 is what I need to do that... but I really don't understand why all of the pins of the BSCANE2 component seem to have ...Read more

fpga - xil_cache error in Xilinx SDK

I am working on a small project of mine on Digilent Atlys and after all of the standard generating the netlist and bitstream, and exporting to SDK, I happen to get a weird error which states that the xil_cache.h is not present anywhere (even though it is there). I need to mention that if I don't add an interrupt controller and a timer it works, but I really do need them.Has anyone encountered this error before?Error Message:08:24:21 **** Build of configuration Debug for project hiworld ****make all 'Building file: ../src/helloworld.c''Invoking...Read more

fpga - Design Flow to create a bootable SPI Flash (PROM File) for a Xilinx Spartan-6 containing Configuration bitsream AND Microblaze software

I would like to know the proper procedure to create a PROM file (.MCS) for a serial SPI Flash that include BOTH the FPGA configuration bitstream and the software to be used by the Microblaze processor. This is assuming my hardware and software design is all done.I am using a Xilinx Spartan-6 evaluation board, the SP605, which has several non-volatile memory devices and I wish to use the serial SPI Flash to store BOTH the FPGA bitstream AND the Microblaze's software that needs to be loaded into memory. I am able to achieve this only if the Micro...Read more

fpga - numato mimas v2 interfacing with ddr ram

I am a newbie here, I used and have my hand on arduino, but now I got task of taking 3000 samples of waveform with 100MSPS with an adc.As this was impossible with arduino and most of the controller I switch to FPGA,And bought NUMATO MIMAS v2 (As it has on board 512Mb DDR RAM, which is capable of handling that much fast operation.)And also bought AD9283 along with it as it has 100MSPS 8bit adc output.I am using Xilinx ISE, and using Verilog(No specific reason for it).My PROBLEM is I am unable to interface that inbuilt DDR ram and communicate wi...Read more