computer architecture - How/does DMA handle multiple concurrent transfers?

I am working on implementing a VM and trying to model all the different hardware components as accurately as possible, just for pure learning purposes.My question is, how does a DMA device handle multiple concurrent transfer requests? From what I understand a DMA device has several registers to set the location in memory, the type of operation (read or write) and the number of bytes, so what happens when the CPU requests an operation from DMA, puts the thread to sleep and then the next thread that runs also requests a DMA operation while the pr...Read more

computer architecture - Interrupt time in DMA operation

I'm facing difficulty with the following question :Consider a disk drive with the following specifications . 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever 1 byte word is ready it is sent to memory; similarly for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory Cycle time is 40 ns. The maximum percentage of time that the CPU gets blocked during DMA operation is?the solution to this question provided o...Read more

computer architecture - Different schemes of two-bit branch prediction

Why do we have two versions of 2-bit branch prediction as shown in the figures below?First SchemeAlternate SchemeIn the first scheme, the transition is from weakly not taken to weakly taken and weakly taken to weakly not taken if it is misprediction but in the alternative scheme, the transition is from weakly not taken to strongly taken and from weakly taken to strongly not taken if it is misprediction. How does one scheme compared to the other or does both give the same accuracy?...Read more

computer architecture - Understanding stalls and branch delay slots

I am taking a course on Computer Architecture. I found this website from another University which has notes and videos which are helping me thus far: CS6810, Univ of Utah. I am working through some old homework assignments posted on that site, in particular this one. I am trying to understand pipelining and related concepts, specifically stalls and branch delay slots.I am looking now at the first question from that old homework assignment and am unsure of how to do these problems. The question is as follows: Consider the following code segmen...Read more

computer architecture - 2-way set associative cache hit/miss checking

I have 256 blocks with 16 byte per block. I'm trying to define miss or hit the hexadecimal addresses according to 2-way set associative cache. I doubt that the second can be miss because of 2-way set associative? I think as hit but I'm not sure.2ABC10A22ABC10A74BBC10A02ABC10A9So If I have 16 bytes per block, I have 2^4 then 4 bits that means respectively my offsets are 2, 7, 0, 9. If I have 256 blocks, I have 2^8 then 8 bits index that means 0A the remains are tags. I think I'm right up to here. So I get the table but I'm not for miss/hit part...Read more

computer architecture - When an interrupt occurs, what happens to instructions in the pipeline?

Assume a 5 stage pipeline architecture (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back).There are 4 instructions that has to be executed.(These sample instruction are not accurate, but I believe the point would be understood)In the fifth clock cycle, these instruction will be in pipeline as shown below.Add a, b, c [IF ID EX MEM WB]Add a, b, d [IF ID EX MEM]Add a, b, e [IF ID EX]Add a, b, f [IF ID]Now if an hardware interrupts occur what happens to these instructio...Read more

computer architecture - What is the speedup? Can't understand the solution

I'm going through a Computer Architecture MOOC on my time. There is a problem I can't solve. The solution is provided but I can't understand the solution. Can someone help me out. Here is the problem and the solution to it: Consider an unpipelined processor. Assume that it has 1-ns clock cycle and that it uses 4 cycles for ALU operations and 5 cycles for branches and 4 cycles for memory operations. Assume that the relative frequencies of these operations are 50 %, 35 % and 15 % respectively. Suppose that due to clock skew and set up, pip...Read more

computer architecture - In FSMs does one State last one clock cycle or more?

Need to design a simple one for school. More specifically a Moore FSM. Im not sure how state transitions happen, is it next state each clock?I need to know because im wondering if i can shift a register and add a value to it, all in the same state... Could use wave edges?EDIT:I have to design the ALU part with registers as a schematic from gate-level, so no target CPU.I made the algorith diagram, then put states to function blocks according Moore FSM rules. each block of operations gets one state. For instance in a state S1, i have the followin...Read more

computer architecture - Making a pipelined processor with instructions issued in alternate clock cycles

Why can't we design a (semi)pipelined processor that issues instruction at every alternate clock tick, instead of the pipelined processor that issues instruction at every clock tick?Having the instructions wait would probably reduce the hazards and stalls that we try to solve in a complicate way. It could completely eliminate the branch stalls and thus save the expensive pipeline flush....Read more

computer architecture - Static Hazard 1 and One Circuit Problems?

I read about Static Hazard. We know Static 1-hazard is: Input change causes output to go from 1 to 0 to 1. My note covers a Circuit as follows: My notes says: When B=C=D=1, for any changes in A values, it's probable to have Static Hazard 1. But I think: for 1 to 0 transition of A static hazard 1 can be observed. for 0 to 1 transition of A no hazard can be observed.anyone could describe my sentence is correct or my note say the correct sentence. which of them is correct ? why? Thanks....Read more

computer architecture - MIX or MMIX - what is the best

Hi my first question …I start reading ‘The Art of Computer Programming’. I know it’s hard. First I decide to lean the language of book – I start with MIX. I made some exercises and I think I can manages with programs in the book. But the problem is everywhere I wrote, MIX is old, learn MMIX and so on. OKS, but why - this my question? I am learning 1 moth MIX and I start to understand problems in book and now stop working and start learning new ASM again, why? Say, MIX is old, but all code in the book is MIX if I spend time to learn MMIX I have...Read more